document number: 91230 www.vishay.com s-81271-rev. a, 16-jun-08 1 power mosfet IRFP450A, sihfp450a vishay siliconix features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterized capacitance and avalanche voltage and current ? effective c oss specified ? lead (pb)-free available applications ? switch mode power supply (smps) ? uninterruptable power supply ? high speed power switching typical smps topologies ? two transistor forward ? half bridge, full bridge ? pfc boost notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 7.8 mh, r g = 25 , i as = 14 a (see fig. 12). c. i sd 14 a, di/dt 130 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) 500 r ds(on) ( )v gs = 10 v 0.40 q g (max.) (nc) 64 q gs (nc) 16 q gd (nc) 26 configuration single n -channel mosfet g d s to-247 g d s a v aila b le rohs* compliant ordering information package to-247 lead (pb)-free IRFP450Apbf sihfp450a-e3 snpb IRFP450A sihfp450a absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 14 a t c = 100 c 8.7 pulsed drain current a i dm 56 linear derating factor 1.5 w/c single pulse avalanche energy b e as 760 mj repetitive avalanche current a i ar 14 a repetitive avalanche energy a e ar 19 mj maximum power dissipation t c = 25 c p d 190 w peak diode recovery dv/dt c dv/dt 4.1 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91230 2 s-81271-rev. a, 16-jun-08 IRFP450A, sihfp450a vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. c. c oss eff. is a fixed capacitance that gi ves the same charging time as c oss while v ds is rising from 0 to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -40 c/w case-to-sink, flat, greased surface r thcs 0.24 - maximum junction-to-case (drain) r thjc -0.65 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.58 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v - - 25 a v ds = 400 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 8.4 a b --0.40 forward transconductance g fs v ds = 50 v, i d = 8.4 a b 7.8 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 2038 - pf output capacitance c oss - 307 - reverse transfer capacitance c rss -10- output capacitance c oss v gs = 0 v; v ds = 1.0 v, f = 1.0 mhz 2859 output capacitance c oss v gs = 0 v; v ds = 400 v, f = 1.0 mhz 81 effective output capacitance c oss eff. v gs = 0 v; v ds = 0 v to 400 v c 96 total gate charge q g v gs = 10 v i d = 14 a, v ds = 400 v, see fig. 6 and 13 b --64 nc gate-source charge q gs --16 gate-drain charge q gd --26 turn-on delay time t d(on) v dd = 250 v, i d = 14 a, r g = 6.2 , r d = 17 , see fig. 10 b -15- ns rise time t r -36- turn-off delay time t d(off) -35- fall time t f -29- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --14 a pulsed diode forward current a i sm --56 body diode voltage v sd t j = 25 c, i s = 14 a, v gs = 0 v b --1.4 v body diode reverse recovery time t rr t j = 25 c, i f = 14 a, di/dt = 100 a/s b - 487 731 ns body diode reverse recovery charge q rr -3.95.8c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) s d g
document number: 91230 www.vishay.com s-81271-rev. a, 16-jun-08 3 IRFP450A, sihfp450a vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
www.vishay.com document number: 91230 4 s-81271-rev. a, 16-jun-08 IRFP450A, sihfp450a vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
document number: 91230 www.vishay.com s-81271-rev. a, 16-jun-08 5 IRFP450A, sihfp450a vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circui t fig. 12b - unclamped inductive waveforms p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f a r g i as 0.01 t p d.u.t. l v ds + - v dd dri v er 15 v 20 v i as v ds t p
www.vishay.com document number: 91230 6 s-81271-rev. a, 16-jun-08 IRFP450A, sihfp450a vishay siliconix fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 12d - typical drain-to-source voltage vs. avalanche current fig. 13b - gate charge test circuit q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91230 www.vishay.com s-81271-rev. a, 16-jun-08 7 IRFP450A, sihfp450a vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91230. p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g
document number: 91360 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-247ac (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. contour of slot optional. 3. dimension d and e do not include mold flash. mold flash shal l not exceed 0.127 mm (0.005") per side. these dimensions are me asured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions d1 and e1. 5. lead finish uncontrolled in l1. 6. ? p to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. outline conforms to jedec outline to-247 with exception of dimension c. 0.10 a c mm e e/2 (2) (4) r/2 b 2 x r s d see v ie w b 2 x e b 4 3 x b 2 x b 2 l c l1 1 2 3 q d a a2 a a a1 c ? k b d mm a ?p (dat u m b) ?p1 d1 4 e1 0.01 b d mm v ie w a - a thermal pad d2 dde e c c v ie w b ( b 1, b 3, b 5) base metal c1 ( b , b 2, b 4) section c - c, d - d, e - e (c) planting 4 3 5 7 5 5 millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 4.65 5.31 0.183 0.209 d2 0.51 1.30 0.020 0.051 a1 2.21 2.59 0.087 0.102 e 15.29 15.87 0.602 0.625 a2 1.50 2.49 0.059 0.098 e1 13.72 - 0.540 - b 0.99 1.40 0.039 0.055 e 5.46 bsc 0.215 bsc b1 0.99 1.35 0.039 0.053 ? k 0.254 0.010 b2 1.65 2.39 0.065 0.094 l 14.20 16.10 0.559 0.634 b3 1.65 2.37 0.065 0.093 l1 3.71 4.29 0.146 0.169 b4 2.59 3.43 0.102 0.135 n 7.62 bsc 0.300 bsc b5 2.59 3.38 0.102 0.133 ? p 3.56 3.66 0.140 0.144 c 0.38 0.86 0.015 0.034 ? p1 - 7.39 - 0.291 c1 0.38 0.76 0.015 0.030 q 5.31 5.69 0.209 0.224 d 19.71 20.70 0.776 0.815 r 4.52 5.49 0.178 0.216 d1 13.08 - 0.515 - s 5.51 bsc 0.217 bsc ecn: s-81920-rev. a, 15-sep-08 dwg: 5971
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